Array self repair using built-in self test techniques
US7257745B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Oct 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Using single-bit MISR error evaluation an ABSIT test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.