Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor
US7259054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Oct 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.