Nonvolatile semiconductor memory device and its fabrication method
US7259422B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2007 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jan 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.