Integrated circuit yield enhancement using Voronoi diagrams

US7260790B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert J. Allen · South Harwich, US
• Michael S. Gray · Saint Albans, US
• Jason D. Hibbeler · Williston, US
• Mervyn Y. Tan · Colchester, US
• Robert F. Walker · South Burlington, US

Key dates

• Filing date: Apr 27, 2004
• Grant date: Aug 21, 2007
• Expiry date: May 31, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/398
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.