Terraced film stack
US7262053B2 · kind B2 · utility
3Cited by
0References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Sep 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.