Minimizing resist poisoning in the manufacture of semiconductor devices
US7262129B2 · kind B2 · utility
0Cited by
7References
8Claims
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Assignee
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Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Nov 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.