Power semiconductor packaging method and structure
US7262444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Aug 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.