P-channel MOS transistor and fabrication process thereof
US7262465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
Abstract
A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si layer in correspondence to the channel region via a gate insulation film, and first and second p-type diffusion regions formed in the strained Si layer at respective first and second sides of the channel region, wherein the strained Si layer has first and second sidewall surfaces respectively at the first and second sides thereof, a first SiGe mixed crystal region being formed epitaxially to the SiGe mixed crystal layer in contact with the first sidewall surface, a second SiGe mixed crystal region being formed epitaxially to the SiGe mixed crystal layer in contact with the second sidewall surface, the first and second SiGe mixed crystal regions being in lattice matching with the strained silicon layer respectively at the first and second sidewall surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.