Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
US7263011B2 · kind B2 · utility
4Cited by
10References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Oct 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory block being external to the main memory block. The substitution memory block is arranged to substitute at least one bitline-related or wordline-related set of memory cells being connected to the same bitline or wordline, respectively. Furthermore, the inventive memory circuit comprises redirection means for redirecting the access to a memory cell of the at least one respective substituted set of memory cells to the substitution memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.