Method of fabricating heterojunction devices integrated with CMOS
US7265006B2 · kind B2 · utility
16Cited by
6References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 7, 2005 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Jul 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
Abstract
A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to contact individually each one of a plurality of heterojunction devices or contact a plurality of heterojunction devices in parallel. This method can be used to fabricate three-terminal devices and vertically stacked devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.