Patent · US Expired

Stackable single package and stacked multi-chip assembly

US7265441B2 · kind B2 · utility

7Cited by

6References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Werner Reiss · Bad Feilnbach, DE
Wolfgang Hetzel · Nattheim, DE

Key dates

Filing date	Aug 15, 2005
Grant date	Sep 4, 2007
Priority date	—
Expiry date	Mar 2, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring of the substrate, and a ring surrounding edges of the chip are also included. The ring is formed from an electrically insulating material and includes a plurality of openings, each opening adjacent a substrate contact pad to allow for electrical connection to the chip though the substrate contact pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.