Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules

US7266788B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Anand Haridass · Bengaluru, IN
• Andreas Huber · Holzgerlingen, DE
• Erich Klink · Schenefeld, DE
• Thomas Strach · Wildberg, DE
• Jochen Supper · Herrenberg, DE

Key dates

• Filing date: Jul 19, 2005
• Grant date: Sep 4, 2007
• Expiry date: Jan 12, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.