Methods for elimination of arsenic based defects in semiconductor devices with isolation regions
US7268048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jun 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation. Methods include wet etch procedures featuring hydrofluoric acid and hydrogen peroxide, as well as spin dry and dry etch procedures both employed post hydrofluoric acid treatment to remove re-deposited arsenic based defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.