Tri-gate transistors and methods to fabricate same
US7268058B2 · kind B2 · utility
144Cited by
45References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Feb 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
Abstract
Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.