Memory cell with trench capacitor and vertical select transistor and an annular contact-making region formed between them

US7268381B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Albert Birner · Regensburg, DE
• Matthias Goldbach · Dresden, DE
• Till Schlosser · Dresden, DE

Key dates

• Filing date: Jul 12, 2002
• Grant date: Sep 11, 2007
• Expiry date: Oct 12, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.