JFET structure for integrated circuit and fabrication method
US7268394B2 · kind B2 · utility
3Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jan 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
Abstract
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.