Method and apparatus for built-in self-test (BIST) of integrated circuit device
US7269772B1 · kind B1 · utility
12Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Dec 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit device (200) can include a main portion (204) and a built-in self-test (BIST) portion (204) having outputs coupled to physical input structures (e.g., bond pads) (206) of the integrated circuit device (200). A BIST portion (202) can test timing critical parameters that take into account the effect of input structures (206). A BIST portion (202) can apply BIST test signals with a pipeline structure that can emulate timing parameters, such as a set-up time (Ts) and a clock-to-output time (Tco).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.