Design verification
US7269808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.