Semiconductor device having a bond pad and method therefor

US7271013B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Lois Yong · Austin, US
• Peter R. Harper · معلمی نژاد, US
• Tu-Anh N. Tran · Austin, US
• Jeffrey W. Metz · Round Rock, US
• George R. Leal · Cedar Park, US
• Dieu Van Dinh · Austin, US

Key dates

• Filing date: Dec 10, 2004
• Grant date: Sep 18, 2007
• Expiry date: Oct 11, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.