Inventor · Cedar Park, TX, US

George R. Leal

23Patents
9h-index
31Co-inventors
71Inventor score

Filing activity: Mar 13, 2002 → Sep 10, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US6838776B2 Circuit device with at least partial packaging and method for forming Electricity 237 Expired
US6921975B2 Circuit device with at least partial packaging, exposed active surface and a voltage reference plane Electricity 188 Expired
US6844631B2 Semiconductor device having a bond pad and method therefor Electricity 89 Expired
US7361987B2 Circuit device with at least partial packaging and method for forming Electricity 61 Active
US7405102B2 Methods and apparatus for thermal management in a multi-layer embedded chip structure Electricity 54 Active
US7892882B2 Methods and apparatus for a semiconductor device package with improved thermal performance Electricity 17 Active
US8216918B2 Method of forming a packaged semiconductor device Electricity 17 Active
US8829661B2 Warp compensated package and method Electricity 10 Active
US7271013B2 Semiconductor device having a bond pad and method therefor Electricity 9 Expired
US8349666B1 Fused buss for plating features on a semiconductor die Electricity 7 Active
US7950144B2 Method for controlling warpage in redistributed chip packaging panels Emerging Cross-Sectional Technologies 7 Active
US7528069B2 Fine pitch interconnect and method of making Electricity 7 Expired
US9107303B2 Warp compensated electronic assemblies Electricity 5 Active
US8072062B2 Circuit device with at least partial packaging and method for forming Electricity 2 Active
US9142434B2 Method for singulating electronic components from a substrate Electricity 2 Active
US8368172B1 Fused buss for plating features on a semiconductor die Electricity 2 Active
US8877523B2 Recovery method for poor yield at integrated circuit die panelization Electricity 2 Active
US10424521B2 Programmable stitch chaining of die-level interconnects for reliability testing Electricity 1 Active
US8970026B2 Methods and structures for reducing stress on die assembly Electricity 0 Active
US9159643B2 Matrix lid heatspreader for flip chip package Electricity 0 Active
US7553753B2 Method of forming crack arrest features in embedded device build-up package and package thereof Electricity 0 Active
US7579219B2 Semiconductor device with a protected active die region and method therefor Electricity 0 Active
US9640469B2 Matrix lid heatspreader for flip chip package Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.