Integrated circuit having a non-volatile memory with discharge rate control and method therefor
US7272053B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Sep 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes, for example, a plurality of parallel-connected transistors (112) coupled between the array (12) of non-volatile memory cells and a power supply terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.