Methods and apparatus for incorporating IDDQ testing into logic BIST
US7272767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Nov 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG) values. The pseudo-random vectors generated by the set of PRPG values are simulated, and those vectors best suited for an IDDQ test are selected. Each of the IDDQ vectors are identified in a test pattern. During subsequent testing, an IDDQ test of the semiconductor chip can be performed whenever the current test vector applied by the logic BIST corresponds to one of the predetermined IDDQ states. A single test pattern based upon vectors generated by the logic BIST module can therefore be used to perform both IDDQ and stuck-at testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.