Cache directory array recovery mechanism to support special ECC stuck bit matrix
US7272773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2003 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.