Formation of fully silicided (FUSI) gate using a dual silicide process
US7273777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.