Patent · US Expired

Memory cell array and method of forming the same

US7274060B2 · kind B2 · utility

8Cited by

3References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martin Popp · Dresden, DE
Frank Jakubowski · Dresden, DE
Juergen Holz · Munich, DE
Lars Heineck · Dresden, DE

Key dates

Filing date	Jun 15, 2005
Grant date	Sep 25, 2007
Priority date	—
Expiry date	Jul 26, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.