Memory cell

US7274069B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Joachim Deppe · Dresden, DE
• Christoph Kleint · Dresden, DE
• Christoph Ludwig · Radeberg, DE

Key dates

• Filing date: Aug 5, 2004
• Grant date: Sep 25, 2007
• Expiry date: Aug 5, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.