Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof
US7274088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Aug 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.