System, method and program product for well-bias set point adjustment
US7274247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Oct 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.