Non-volatile memory and method of controlling the same
US7274592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2006 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single cell that has a gate insulating film formed with an ONO film is provided in a region in which two bit lines cross one word line. The single cell is a four-bit multi-value cell, and has four charge accumulation regions. Two plug-like control electrodes are provided in the region surrounded by the word line and the bit lines. A bias is applied to one of the plug-like control electrodes and the word line so that the portion on the surface of the semiconductor substrate that is located immediately below the word line and corresponds to the location of the bias-applied control electrode is put into an accumulation state or a depletion state. In this manner, the width of the channel is adjusted, and the charge holding state of each of the four charge accumulation regions is controlled through the channel width adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.