Clock duty cycle based access timer combined with standard stage clocked output register
US7275194B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Nov 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31727
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.