Reduction of dopant loss in a gate structure
US7276408B2 · kind B2 · utility
1Cited by
14References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2003 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Oct 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.