Die level metal density gradient for improved flip chip package reliability
US7276435B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2006 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Jun 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.