Power savings in active standby mode
US7277333B2 · kind B2 · utility
69Cited by
16References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2005 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.