System-level test architecture for delivery of compressed tests

US7278123B2 · kind B2 · utility

Assignee

• NEC Laboratories America, Inc. · US

Inventors

• Srivaths Ravi · Plainsboro, US
• Anand Raghunathan · Plainsboro, US
• Loganathan Lingappan · Princeton, US
• Srimat Chakradhar · Manalapan, US
• Niraj K. Jha · Princeton, US

Key dates

• Filing date: Mar 9, 2004
• Grant date: Oct 2, 2007
• Expiry date: Mar 9, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318547
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.