Method to reduce stacking fault nucleation sites and reduce Vf drift in bipolar devices
US7279115B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Mar 27, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and subsurface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.