Apparatus and methods for detection of systematic defects
US7280945B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2002 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Jul 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318364
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns si…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.