Indranil De
115Patents
8h-index
56Co-inventors
83Inventor score
Filing activity: Jul 1, 2002 → Jun 12, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7280945B1 | Apparatus and methods for detection of systematic defects | Physics | 105 | Expired |
| US6861666B1 | Apparatus and methods for determining and localization of failures in test structures using voltage contrast | Physics | 99 | Expired |
| US9496119B1 | E-beam inspection apparatus and method of using the same on various integrated circuit chips | Electricity | 77 | Active |
| US9799575B2 | Integrated circuit containing DOEs of NCEM-enabled fill cells | Electricity | 17 | Active |
| US9805994B1 | Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads | Electricity | 13 | Active |
| US9870962B1 | Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Electricity | 12 | Active |
| US9627370B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 11 | Active |
| US8770143B2 | Multi-region processing system | Emerging Cross-Sectional Technologies | 9 | Active |
| US10593604B1 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells | Electricity | 8 | Active |
| US8278735B2 | Yttrium and titanium high-k dielectric films | Electricity | 6 | Active |
| US7560939B1 | Electrical defect detection using pre-charge and sense scanning with prescribed delays | Physics | 6 | Active |
| US8881677B2 | Shadow mask for patterned deposition on substrates | Chemistry; Metallurgy | 5 | Active |
| US9627371B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 5 | Active |
| US8882917B1 | Substrate processing including correction for deposition location | Physics | 5 | Active |
| US7660687B1 | Robust measurement of parameters | Electricity | 4 | Active |
| US10978438B1 | IC with test structures and E-beam pads embedded within a contiguous standard cell area | Electricity | 4 | Active |
| US9691672B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Electricity | 4 | Active |
| US9741703B1 | Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells | Electricity | 3 | Active |
| US8039052B2 | Multi-region processing system and heads | Emerging Cross-Sectional Technologies | 3 | Active |
| US9773774B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells | Electricity | 3 | Active |
| US8956952B2 | Multilayer substrate structure and method of manufacturing the same | Chemistry; Metallurgy | 3 | Active |
| US10096530B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells | Electricity | 3 | Active |
| US10199283B1 | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage | Electricity | 3 | Active |
| US9653446B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9761575B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.