Method, system and program product for clearing selected storage translation buffer entries
US7281115B2 · kind B2 · utility
9Cited by
16References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Aug 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.