Method of forming an MOS transistor and structure therefor
US7282406B2 · kind B2 · utility
45Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2006 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Mar 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.