Method of manufacturing a nonvolatile semiconductor memory device
US7282411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jan 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate, insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.