Method and device for generating a clock signal using a phase difference signal and a feedback signal
US7282999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Sep 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a device for generating a clock signal (Fout) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (Fin) and a feedback signal (Ffb) derived from the clock signal (Fout) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator (5) is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (Fout). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.