System and method for matching resistance in a non-volatile memory
US7283396B2 · kind B2 · utility
5Cited by
6References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Dec 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.