Method for forming an ESD protection circuit

US7285458B2 · kind B2 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Indrajit Manna · Singapore, SG
• Lo Keng Foo · Singapore, SG
• Tan Pee Ya · Singapore, SG
• Raymond Filippi · Singapore, SG

Key dates

• Filing date: Feb 11, 2004
• Grant date: Oct 23, 2007
• Expiry date: Oct 16, 2025

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T29/49117

Abstract

An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.