Ferroelectric memory devices having expanded plate lines
US7285810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2004 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.