Bit line selection transistor layout structure
US7286396B2 · kind B2 · utility
4Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2005 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Oct 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.