Semiconductor device having trench isolation for differential stress and method therefor
US7288447B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Jun 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.