Method of fabricating analog capacitor using post-treatment technique
US7288453B2 · kind B2 · utility
9Cited by
3References
11Claims
0Family size
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Key dates
| Filing date | Feb 23, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Feb 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0234
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.