Overlay mark for measuring and correcting alignment errors
US7288848B2 · kind B2 · utility
3Cited by
4References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Feb 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.