Optimization algorithm to optimize within substrate uniformities
US7289865B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Nov 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to optimize semiconductor processing equipment (hardware settings and process conditions) to minimize non-uniformities within a wafer based on linescan measurements and a calculation of or prediction for a polar map. Measurements of a metrology value are taken at a number of points along a linescan (or two orthogonal linescans) on the wafer surface for a number of wafer processed in a set of experiments in which one equipment setting or process parameter is adjusted per experiment. The raw data are then normalized and weighted in accordance with the radial distance from the center of the wafer. Standard deviations of different metrology values within the wafer are then calculated. The setting can then be further adjusted to predict and to minimize the standard deviations, and therefore non-uniformity of the metrology values within the wafer, using the method without processing any additional test wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.