Simulating topography of a conductive material in a semiconductor wafer
US7289933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Nov 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.